Musings about disciplined OCXO hold-over

I have been trying to fix a minor shortcoming in my locked 100MHz OCXO project.  If the reference signal is lost, the PLL either starts hunting in a sawtooth pattern, so the output frequency swings a few Hz either side of the free-running frequency, or it goes to one end of the VCO range and jams there.  I have a sort-of-OK workaround, which is to put the PLL charge pump into power-down mode on loss of reference (or loss of lock signal of that reference when it is the 10MHz GPSDO), and trickle a fixed DC level to the loop filter.

I have a 22-turn 5k pot across the low-noise reference supply, with a 10M resistor from the wiper to the junction of the charge pump output and the loop filter input.  Under normal operation, this has negligible effect, but when the charge-pump goes tristate, the voltage on the loop filter capacitors settles to the value set by the 5k pot. The time-constant is very long (CR=10M x 22u, about 3 mins) so there is no sign of a step when the thing goes tristate, and if I’ve tweaked it correctly, the 100MHz output just stays rock-solid to a few parts per billion.

However, there are some measurable variations of reference voltage over each 24 hour period (measured using a 6.5 digit Fluke DVM with GPIB), I guess the cause could be the slow diurnal variation of room temperature, despite the thick expanded polystyrene insulation around the OCXO.  The variation is tiny though, so I wouldn’t be able to measure it easily using a 10-bit ADC in a PIC unless I used an amplifier with x10 to x100 gain and a DC offset.

I sort of imagine a solution where I store the last 24 hours of measured voltage changes at the VCO pin, with an FET-input precision opamp zeroed to the mean lock voltage, then measure the output of the opamp with a 12-bit ADC in a PIC with Flash/EEPROM.  When the lock is lost and the charge-pump goes tristate, I would feed the same voltage from a DAC or PWM output into the loop filter through a 10M resistor.  It would then start to follow the delta pattern from the previous 24 hours, but starting from the current measured value.

The thing would be rather like the current manual solution, but trimmed every ten minutes or so to ensure the holdover voltage is always just about right.  It would automagically compensate for ageing and adapt to seasonal changes, although not to weird weather events. I guess it might be necessary to use an amplifier with a gain of 0.1 to 0.01 and a trimmable offset to get sufficient resolution from a typical PIC DAC/PWM, or perhaps it would be possible to use software dithering for interpolation?  I’d worry about spurs then, but if the time constant is 220s, then a 1Hz randomised dither rate won’t cause any fixed spurs that matter.

I can see it might be necessary to do something a bit cleverer than just outputting the “right” value in the hope that it might give the desired voltage on the loop filter caps.  It might be better to have a simple digital control loop to set the output voltage so that the measured voltage matches the required value.  Just a detail really.

The U-Blox LEA-M8F implements holdover somehow, does anyone have any references for other ways to implement PLL holdover?  The only recent refs I can find are all behind IEEE paywalls.  Does anyone have access to the full text of the Bourke and Penrod paper “An Analysis of a Microprocessor Controlled Disciplined Frequency Standard” ( 37th Annual Symposium on Frequency Control; 1983, p485-491)? [sorry it is behind the IEEE paywall]

Yes I *KNOW* this is overkill for this application and that <10ppb holdover is fine for all practical purposes.  This is about striving for a bit of engineering magic to make me happy.  Fun beats boring old “It’ll do” practicality every time.  In terms of hardware, it will only need an SOT23 op-amp and a slightly better-spec PIC than the one I am using already for monitoring and display, so the additional physical complexity is minimal.

Leave a Reply

Your email address will not be published. Required fields are marked *