Following intricate discussions on the RSGB Tech Yahoo group, I have been working on the detailed design for a phase-locked loop to lock a Valpey-Fisher VFT-22H 100MHz OCXO to my Efratom Rubidium reference clock running at 10MHz. While I am waiting for bits and boards to be delivered, I decided to take the opportunity to learn how to use some circuit modelling software.
This model was built using the Sue2 schematic capture element of the CppSim package from Michael Perrott.
The schematic uses standard building blocks which are then compiled as C++ objects to maximise the speed of the models. So I could try out CppSim, I have created a model of the XOR-based version of the PLL.
Step 1: Schematic capture using Sue2
Next step is to compile and run the simulation in CppSim after selecting the time steps and which elements should be probed in a test.par parameter file. In this case I am interested in the ref, vin, out and div signals.
Now to run the simulation. This is a huge computation with 5 billion steps at 1ns intervals, but that is too much for the graphical display tools, so I have to select shorter time periods of a few tens of million steps. The simulation took 30 mins on my desktop PC.
Next step is to display the captured signals in the probe list which are saved in the .FST file by CppSim, using GTKWave. The initial phase offset between the ref and div signals was about 20 degrees. After 5 seconds, the phase has pulled to 90 degrees and the vin has settled to a sawtooth with a mean value of -0.19 mV and a peak to peak value of 4.5 microvolts. Top trace shows the 100MHz out, next is the 10MHz ref, then the divider output and finally the vin at the vctrl pin of the OCXO. Signals are referred to 0V, in the real system the ref will be 2.5V.
This is using a simple RC filter with a time constant of 1/30 s.
At the beginning, the vin starts at 0.0 V and pulls negative to try to get to 90 degree phase difference:
Running a sample once per microsecond for 5s shows an overdamped response as expected from a simple RC filter:
Initially, the voltage drops to -0.5 but pulls in so that at 5s, the offset is only 0.2mV, better than 1mHz, which is better than the precision of the reference. In reality there will be an offset caused by the non-infinite input resistance of the OCXO.
Next step will be to model the response using a lead-lag filter and a resistive input with a small DC offset error.
Verdict on CppSim software (which is freeware) is very positive so far.